EP2A25F672C7 vs EP2A25F672I-9 Comparison
Detailed side-by-side comparison of EP2A25F672C7 by Altera and EP2A25F672I-9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A25F672C7
EP2A25F672C7 - APEX II FPGA, 25K LE, 492 I/O, 672-BGA | Altera
EP2A25F672C7 NrndIntel
EP2A25F672I-9
EP2A25F672I-9 - APEX II 25K LUT FPGA, 672-BGA | Intel / Altera
EP2A25F672I-9 ObsoleteSpecification Comparison
| Parameter | EP2A25F672C7 | EP2A25F672I-9 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $118.00 | $195.00 |
| Product Family | APEX II | β |
| Logic Elements | 25,000 | β |
| Maximum System Gates | 1,650,000 | [DATA_NEEDED: maximum system gates] |
| Maximum RAM Bits | 422,976 | β |
| User I/O Count | 492 | β |
| Package | 672-ball FCBGA (FineLine BGA) | 672-pin FCBGA (FineLine BGA) |
| Process Technology | 0.15-um all-layer copper, up to 8 metal layers | 0.18 Β΅m CMOS |
| Supply Voltage (Core) | 1.5 V | β |
| LVDS Data Rate | 1 Gbps per channel (True-LVDS) | β |
| I/O Standards Supported | LVDS, LVPECL, PCML, HyperTransport | β |
| Operating Temperature | 0C to +85C (Commercial) | β |
| Speed Grade | -7 | -9 |
| Configuration Mode | Passive Serial, Passive Parallel, JTAG | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Embedded System Blocks (ESB) | Yes - RAM, ROM, CAM, multiplier support | β |
| Family | β | APEX II |
| Logic Elements (typical) | β | 25,000 |
| Embedded System Blocks (ESB) Memory | β | 1,125 Kbits |
| Maximum User I/O Pins | β | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | β | 4 |
| Core Voltage | β | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C junction) |
| Mounting Type | β | Surface Mount (BGA) |
| Moisture Sensitivity Level (MSL) | β | 3 (per Vyrian listing) |
| Peak Reflow Temperature | β | 220 Β°C (per Vyrian listing) |
| Configuration Method | β | JTAG / serial configuration EPROM |
| Supported I/O Standards | β | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | β | Obsolete - consult Altera / Intel FPGA archive for documentation |