EP2A25F672C7N vs EP2A25F672C9N Comparison
Detailed side-by-side comparison of EP2A25F672C7N by Altera and EP2A25F672C9N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672C7N | EP2A25F672C9N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $195.00 |
| Family | APEX II | APEX II |
| Logic Elements | 24,320 cells | β |
| System Gates | Approximately 900,000 | Approx. 900000 |
| User I/Os | 492 | β |
| Propagation Delay (tPD) | 1.69 ns | β |
| Internal Operating Frequency | Up to 500 MHz | β |
| Core Voltage (VCCINT) | 1.5 V | β |
| Process Technology | 0.15 Β΅m all-layer copper (up to 8 metal layers) | 0.15 Β΅m all-layer copper, up to 8 metal layers |
| Logic Family | CMOS | CMOS |
| Package Type | 672-ball FC-FBGA (FineLine BGA) | β |
| Package Body Size | 27 x 27 mm | β |
| Ball Pitch | 1.0 mm | β |
| Operating Temperature | 0 Β°C to 85 Β°C (commercial) | 0 Β°C to +85 Β°C (commercial, C9 grade) |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | β |
| Programmable Logic Type | Loadable PLD (in-system programmable) | β |
| Embedded Memory | Embedded System Blocks (ESB) configurable as dual-port RAM/ROM | Enhanced System Blocks (ESBs) for dual-port RAM |
| PLLs | Up to 4 | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Compliant (per distributor listings) |
| Logic Elements / Cells | β | 24320 |
| Maximum User I/O | β | 492 |
| Operating Frequency | β | 236 MHz |
| Core Supply Voltage (VCCINT) | β | 1.425 V to 1.575 V (nominal 1.5 V) |
| Package | β | 672-ball FineLine BGA (F672), 27 Γ 27 mm, 1.00 mm pitch |
| Seated Height (max) | β | 2.100 mm |
| Propagation Delay | β | 2.23 ns |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport |
| LVDS Data Rate | β | Up to 1 Gbps (True-LVDS) |
| Configuration Interface | β | Serial / Parallel PROM, JTAG, passive parallel (enhanced) |
| Design Software | β | Quartus II (v5.1 or later) |