EP2A25F672C8 vs EP2A25F672C9 Comparison
Detailed side-by-side comparison of EP2A25F672C8 by Altera and EP2A25F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A25F672C8
EP2A25F672C8 - APEX II FPGA 492 I/O 672-FBGA | Intel / Altera
EP2A25F672C8 ObsoleteSpecification Comparison
| Parameter | EP2A25F672C8 | EP2A25F672C9 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $951.18 | $700.00 |
| Family | APEX II (EP2A25) | APEX II |
| Logic Elements | 25,000 (typical gates) | β |
| Maximum System Gates | 40,960 | β |
| Macrocells / Embedded Logic | 2,432 macros | β |
| User I/O Count | 492 | β |
| Package | 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) | 672-ball FCBGA (FineLine BGA) |
| Propagation Delay (tpd) | 1.69 ns | β |
| Speed Grade | C8 | β |
| Operating Temperature | 0 C to 85 C (commercial) | 0Β°C to 85Β°C (Commercial) |
| Process Technology | 0.15 microm CMOS, 8-layer copper interconnect | 0.15 Β΅m all-layer copper, up to 8 metal layers |
| I/O Standards Supported | LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL | β |
| LVDS Data Rate | 1 Gbps | β |
| PLL Count | 4 | β |
| Embedded Memory | ESB blocks (dual-port RAM, FIFO, CAM, ROM) | ESBs for dual-port RAM, ROM, FIFO |
| I/O Banks | 16 | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (legacy product) | [DATA_NEEDED] |
| Logic Elements (LE) | β | Approximately 25,000 |
| Macro Cells | β | 2432 |
| User I/O | β | 492 |
| Package Dimensions | β | 27 mm x 27 mm |
| Ball Pitch | β | 1.0 mm |
| Logic Family | β | CMOS |
| Propagation Delay | β | 1.69 ns |
| Supply Voltage | β | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | β | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | β | Passive Serial, Passive Parallel Synchronous, JTAG |