EP2A25F672C8 vs EP2A25F672I-9 Comparison
Detailed side-by-side comparison of EP2A25F672C8 by Altera and EP2A25F672I-9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A25F672C8
EP2A25F672C8 - APEX II FPGA 492 I/O 672-FBGA | Intel / Altera
EP2A25F672C8 ObsoleteIntel
EP2A25F672I-9
EP2A25F672I-9 - APEX II 25K LUT FPGA, 672-BGA | Intel / Altera
EP2A25F672I-9 ObsoleteSpecification Comparison
| Parameter | EP2A25F672C8 | EP2A25F672I-9 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $951.18 | $195.00 |
| Family | APEX II (EP2A25) | APEX II |
| Logic Elements | 25,000 (typical gates) | β |
| Maximum System Gates | 40,960 | [DATA_NEEDED: maximum system gates] |
| Macrocells / Embedded Logic | 2,432 macros | β |
| User I/O Count | 492 | β |
| Package | 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) | 672-pin FCBGA (FineLine BGA) |
| Propagation Delay (tpd) | 1.69 ns | β |
| Speed Grade | C8 | -9 |
| Operating Temperature | 0 C to 85 C (commercial) | β |
| Process Technology | 0.15 microm CMOS, 8-layer copper interconnect | 0.18 Β΅m CMOS |
| I/O Standards Supported | LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL | β |
| LVDS Data Rate | 1 Gbps | β |
| PLL Count | 4 | β |
| Embedded Memory | ESB blocks (dual-port RAM, FIFO, CAM, ROM) | β |
| I/O Banks | 16 | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | Non-compliant (legacy product) | [DATA_NEEDED: RoHS status] |
| Logic Elements (typical) | β | 25,000 |
| Embedded System Blocks (ESB) Memory | β | 1,125 Kbits |
| Maximum User I/O Pins | β | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | β | 4 |
| Core Voltage | β | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C junction) |
| Moisture Sensitivity Level (MSL) | β | 3 (per Vyrian listing) |
| Peak Reflow Temperature | β | 220 Β°C (per Vyrian listing) |
| Configuration Method | β | JTAG / serial configuration EPROM |
| Supported I/O Standards | β | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | β | Obsolete - consult Altera / Intel FPGA archive for documentation |