EP2A25F672C9 vs EP2A25F672C8 Comparison
Detailed side-by-side comparison of EP2A25F672C9 by Altera and EP2A25F672C8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672C9 | EP2A25F672C8 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $700.00 | $951.18 |
| Family | APEX II | APEX II (EP2A25) |
| Logic Elements (LE) | Approximately 25,000 | β |
| Macro Cells | 2432 | β |
| User I/O | 492 | β |
| Package | 672-ball FCBGA (FineLine BGA) | 672-FBGA (FineLine BGA, 27x27 mm, 1.0 mm pitch) |
| Package Dimensions | 27 mm x 27 mm | β |
| Ball Pitch | 1.0 mm | β |
| Process Technology | 0.15 Β΅m all-layer copper, up to 8 metal layers | 0.15 microm CMOS, 8-layer copper interconnect |
| Logic Family | CMOS | β |
| Propagation Delay | 1.69 ns | β |
| Operating Temperature | 0Β°C to 85Β°C (Commercial) | 0 C to 85 C (commercial) |
| Supply Voltage | [DATA_NEEDED: core VCC voltage] | β |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) | β |
| Configuration | Passive Serial, Passive Parallel Synchronous, JTAG | β |
| Embedded Memory | ESBs for dual-port RAM, ROM, FIFO | ESB blocks (dual-port RAM, FIFO, CAM, ROM) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED] | Non-compliant (legacy product) |
| Logic Elements | β | 25,000 (typical gates) |
| Maximum System Gates | β | 40,960 |
| Macrocells / Embedded Logic | β | 2,432 macros |
| User I/O Count | β | 492 |
| Propagation Delay (tpd) | β | 1.69 ns |
| Speed Grade | β | C8 |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI-X, GTL+, SSTL-2/3, HSTL, LVDS, LVPECL |
| LVDS Data Rate | β | 1 Gbps |
| PLL Count | β | 4 |
| I/O Banks | β | 16 |