EP2A25F672C9 vs EP2A25F672I-9 Comparison
Detailed side-by-side comparison of EP2A25F672C9 by Altera and EP2A25F672I-9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672C9 | EP2A25F672I-9 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $700.00 | $195.00 |
| Family | APEX II | APEX II |
| Logic Elements (LE) | Approximately 25,000 | β |
| Macro Cells | 2432 | β |
| User I/O | 492 | β |
| Package | 672-ball FCBGA (FineLine BGA) | 672-pin FCBGA (FineLine BGA) |
| Package Dimensions | 27 mm x 27 mm | β |
| Ball Pitch | 1.0 mm | β |
| Process Technology | 0.15 Β΅m all-layer copper, up to 8 metal layers | 0.18 Β΅m CMOS |
| Logic Family | CMOS | β |
| Propagation Delay | 1.69 ns | β |
| Operating Temperature | 0Β°C to 85Β°C (Commercial) | β |
| Supply Voltage | [DATA_NEEDED: core VCC voltage] | β |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) | β |
| Configuration | Passive Serial, Passive Parallel Synchronous, JTAG | β |
| Embedded Memory | ESBs for dual-port RAM, ROM, FIFO | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Logic Elements (typical) | β | 25,000 |
| Maximum System Gates | β | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | β | 1,125 Kbits |
| Maximum User I/O Pins | β | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | β | 4 |
| Core Voltage | β | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C junction) |
| Speed Grade | β | -9 |
| Moisture Sensitivity Level (MSL) | β | 3 (per Vyrian listing) |
| Peak Reflow Temperature | β | 220 Β°C (per Vyrian listing) |
| Configuration Method | β | JTAG / serial configuration EPROM |
| Supported I/O Standards | β | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | β | Obsolete - consult Altera / Intel FPGA archive for documentation |