EP2A25F672C9N vs EP2A25F672C9 Comparison

Detailed side-by-side comparison of EP2A25F672C9N by Intel and EP2A25F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP2A25F672C9N EP2A25F672C9
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $195.00 $700.00
Family APEX II APEX II
Logic Elements / Cells 24320 β€”
System Gates Approx. 900000 β€”
Maximum User I/O 492 β€”
Operating Frequency 236 MHz β€”
Core Supply Voltage (VCCINT) 1.425 V to 1.575 V (nominal 1.5 V) β€”
Process Technology 0.15 Β΅m all-layer copper, up to 8 metal layers 0.15 Β΅m all-layer copper, up to 8 metal layers
Package 672-ball FineLine BGA (F672), 27 Γ— 27 mm, 1.00 mm pitch 672-ball FCBGA (FineLine BGA)
Mounting Type Surface Mount (BGA) Surface Mount
Seated Height (max) 2.100 mm β€”
Propagation Delay 2.23 ns 1.69 ns
Logic Family CMOS CMOS
Operating Temperature 0 Β°C to +85 Β°C (commercial, C9 grade) 0Β°C to 85Β°C (Commercial)
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport β€”
LVDS Data Rate Up to 1 Gbps (True-LVDS) β€”
Configuration Interface Serial / Parallel PROM, JTAG, passive parallel (enhanced) β€”
Embedded Memory Enhanced System Blocks (ESBs) for dual-port RAM ESBs for dual-port RAM, ROM, FIFO
Design Software Quartus II (v5.1 or later) β€”
RoHS Status Compliant (per distributor listings) [DATA_NEEDED]
Logic Elements (LE) β€” Approximately 25,000
Macro Cells β€” 2432
User I/O β€” 492
Package Dimensions β€” 27 mm x 27 mm
Ball Pitch β€” 1.0 mm
Supply Voltage β€” [DATA_NEEDED: core VCC voltage]
I/O Standards β€” LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V)
Configuration β€” Passive Serial, Passive Parallel Synchronous, JTAG

Datasheets & Resources

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