EP2A25F672I-9 vs EP2A25F672C9 Comparison
Detailed side-by-side comparison of EP2A25F672I-9 by Intel and EP2A25F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672I-9 | EP2A25F672C9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $700.00 |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | β |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | β |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | β |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | β |
| Number of PLLs | 4 | β |
| Process Technology | 0.18 Β΅m CMOS | 0.15 Β΅m all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | β |
| Operating Temperature Grade | Industrial (-40 Β°C to +100 Β°C junction) | β |
| Speed Grade | -9 | β |
| Package | 672-pin FCBGA (FineLine BGA) | 672-ball FCBGA (FineLine BGA) |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Moisture Sensitivity Level (MSL) | 3 (per Vyrian listing) | β |
| Peak Reflow Temperature | 220 Β°C (per Vyrian listing) | β |
| Configuration Method | JTAG / serial configuration EPROM | β |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | β |
| Logic Elements (LE) | β | Approximately 25,000 |
| Macro Cells | β | 2432 |
| User I/O | β | 492 |
| Package Dimensions | β | 27 mm x 27 mm |
| Ball Pitch | β | 1.0 mm |
| Logic Family | β | CMOS |
| Propagation Delay | β | 1.69 ns |
| Operating Temperature | β | 0Β°C to 85Β°C (Commercial) |
| Supply Voltage | β | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | β | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | β | Passive Serial, Passive Parallel Synchronous, JTAG |
| Embedded Memory | β | ESBs for dual-port RAM, ROM, FIFO |