EP2A40F1020C9 vs EP2A40F1020I9 Comparison
Detailed side-by-side comparison of EP2A40F1020C9 by Intel and EP2A40F1020I9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A40F1020C9
EP2A40F1020C9 - APEX II FPGA 1.5M Gates 38400 Cells 1020-FBGA | Intel
EP2A40F1020C9 ObsoleteAltera
EP2A40F1020I9
EP2A40F1020I9 - APEX II FPGA, 1.5M Gates, 1020-BGA | Altera
EP2A40F1020I9 ObsoleteSpecification Comparison
| Parameter | EP2A40F1020C9 | EP2A40F1020I9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $160.00 | $2,105.00 |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 38,400 | β |
| System Gates | 1,500,000 (1.5M) | 1.5 M |
| Macrocells | 2,560 | β |
| User I/Os | 735 | β |
| Package | 1020-pin FC-FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch | 1020-pin FC-FBGA |
| Process Technology | 0.15-Β΅m CMOS, up to 8-layer all-layer copper metal | 0.15 Β΅m |
| Core Voltage | 1.5 V | 1.5 V |
| Maximum Internal Frequency | 366 MHz | β |
| Propagation Delay | 1.55 ns | β |
| Logic Family | CMOS | β |
| Operating Temperature | 0Β°C to 85Β°C (Commercial) | [DATA_NEEDED: junction temperature range for I9 grade] |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| I/O Standards Supported | LVTTL, LVCMOS, PCI 32/64-bit, PCI-X 133 MHz, AGP, CTT, SSTL-2 / SSTL-3 Class I & II, GTL+, HSTL Class I & II | β |
| Embedded Memory | ESBs (Embedded System Blocks) supporting dual-port RAM, CAM, and product-term logic | ESBs (dual-port RAM / ROM / FIFO) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm RoHS compliance for FC-FBGA] |
| Series | β | EP2A |
| Logic Cells | β | 38,400 |
| Maximum Operating Frequency | β | 366 MHz |
| Pin Count | β | 1020 |
| Temperature Grade | β | Industrial (I9) |
| Logic Element Type | β | 4-input LUT |
| Configuration Method | β | JTAG / passive serial / passive parallel |