EP2A40F1020I9N vs EP2A40F1020C7N Comparison
Detailed side-by-side comparison of EP2A40F1020I9N by Intel and EP2A40F1020C7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A40F1020C7N - APEX II 1.5M Gates FPGA, 735 I/O, FC-FBGA-1020 | Intel
EP2A40F1020C7N ObsoleteSpecification Comparison
| Parameter | EP2A40F1020I9N | EP2A40F1020C7N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $165.00 | $198.00 |
| Family | APEX II | APEX II |
| Device Logic Elements / Cells | 38,400 cells | β |
| System Gates | 1,500,000 (1.5 M) | 1,500,000 (1.5 M) |
| Maximum Operating Frequency | 366 MHz | β |
| Process Technology | 0.15 um CMOS, up to 8 metal layers | β |
| Core Supply Voltage | 1.5 V | 1.5 V nominal (1.425 V β 1.575 V) |
| User I/O Count | 735 bidirectional I/O | β |
| Package | 1020-pin FC-FBGA (Flip-Chip FineLine BGA) | FC-FBGA-1020, 33 Γ 33 mm, 1.0 mm pitch, fine-line |
| Operating Temperature Grade | Industrial (I9 suffix: -40C to +100C per Altera APEX II convention) | β |
| High-Speed I/O Standards | True-LVDS (up to 1 Gbps), LVPECL, PCML, HyperTransport | β |
| Embedded Memory | ESB-based True-Dual-Port/Single-Port RAM, ROM, CAM (bits [DATA_NEEDED: total RAM bits]) | ESB-based, 504 Kbits total |
| Clock Management | PLLs (count [DATA_NEEDED: PLL count]) | β |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous/Synchronous, JTAG | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Lifecycle Status | Obsolete (per distributor listings / Altera APEX II family EOL) | β |
| Technology | β | 0.15 Β΅m all-layer copper CMOS, up to 8 metal layers |
| Logic Elements | β | 38,400 |
| Maximum Internal Performance | β | 562 MHz |
| Propagation Delay | β | 1.55 ns |
| User I/O Pins | β | 735 |
| PLLs | β | 4 |
| Clock Networks | β | 12 |
| True-LVDS Data Rate | β | 1 Gbps |
| Supported I/O Standards | β | True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL |
| Logic Family | β | CMOS |
| Operating Temperature | β | 0 Β°C to +85 Β°C (commercial, C7 grade) |
| Terminal Form | β | BGA ball (flip-chip) |