EP2A40F672C6 vs EP2A40F672C9ES Comparison

Detailed side-by-side comparison of EP2A40F672C6 by Altera and EP2A40F672C9ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP2A40F672C6 EP2A40F672C9ES
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $105.00 $195.00
Family APEX II APEX II
Device EP2A40 β€”
Logic Elements (typical) 40,000 β€”
Maximum System Gates [DATA_NEEDED: maximum system gates] β€”
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count] β€”
Maximum User I/O Pins [DATA_NEEDED: max user I/O count] β€”
Package 672-ball FineLine BGA (FBGA-672) 672-pin FC-FBGA
Speed Grade C6 (commercial) -9
Operating Temperature Commercial (0C to +85C) β€”
Process Technology 0.18-micron CMOS 0.15 Β΅m CMOS
Configuration Memory SRAM-based β€”
JTAG Support Yes (IEEE 1149.1) β€”
PLL Support Yes β€”
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
RoHS Status [DATA_NEEDED: RoHS status] unknown
Lead-Free [DATA_NEEDED: lead-free status] β€”
Lifecycle Obsolete / EOL (per Intel/Altera product discontinuation notice) β€”
Logic Elements β€” 38,400
System Gates β€” 1,500,000
Maximum User I/O β€” 492
Operating Frequency (max) β€” 366 MHz
Core Voltage β€” 1.5 V
Configuration Modes β€” PS, PPS, PPA, JTAG, FPP
Embedded Memory (ESB) β€” Yes (RAM/ROM/CAM)
I/O Standards β€” LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+
Boundary Scan β€” IEEE 1149.1 (JTAG)

Datasheets & Resources

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