EP2A70B724C7N vs EP2A70B724I7 Comparison
Detailed side-by-side comparison of EP2A70B724C7N by Altera and EP2A70B724I7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A70B724I7 - APEX II FPGA 3M Gates 67200 Cells 420MHz 1.5V 724-FCBGA | Intel
EP2A70B724I7 ObsoleteSpecification Comparison
| Parameter | EP2A70B724C7N | EP2A70B724I7 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $188.00 | $198.50 |
| Family | APEX II (EP2A70) | APEX II |
| Device Type | FPGA (Field Programmable Gate Array) | β |
| Technology | 0.15 Β΅m CMOS | β |
| System Gates | 3,000,000 | β |
| Logic Cells / Logic Elements | 67,200 | β |
| Maximum Internal Frequency | 420 MHz | 420 MHz |
| Propagation Delay (typ.) | 2.17 ns | β |
| User I/O Pins | 536 | β |
| Macrocells (memory blocks reference) | 16 | β |
| Core Supply Voltage | 1.5 V nominal | β |
| I/O Supply Voltage | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) | β |
| Operating Temperature | 0 Β°C to +85 Β°C (Commercial) | β |
| Package | 724-pin FCBGA (Flip-Chip BGA) | 724-pin FCBGA (FineLine BGA) |
| Ball Pitch | 1.27 mm | β |
| Seated Height | 3.5 mm | β |
| Mounting Type | Surface Mount | β |
| Configuration Method | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) | β |
| PLL Count | [DATA_NEEDED: PLL count] | β |
| Embedded Memory | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM | [DATA_NEEDED: ESB bits - 429 Kb or similar] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in provided data] |
| Manufacturer | β | Intel (formerly Altera) |
| Logic Elements | β | 67200 |
| Maximum System Gates | β | 3 M |
| Maximum User I/O Pins | β | approximately 422 (724-pin FCBGA) |
| Process Technology | β | 0.15 um CMOS |
| Core Voltage (VCCINT) | β | 1.5 V |
| I/O Voltages Supported | β | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| PLL Blocks | β | 4 |
| True-LVDS Channels | β | 8 |
| Operating Temperature Grade | β | Industrial (-40 C to +100 C case) |
| Configuration Interface | β | JTAG (IEEE 1149.1) / IEEE 1532 ISP |