EP2AGX125EF35C4G vs EP2AGX95EF35C4G Comparison
Detailed side-by-side comparison of EP2AGX125EF35C4G by Intel and EP2AGX95EF35C4G by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2AGX125EF35C4G - Arria II GX FPGA, 118K LEs, 1152-FCBGA | Intel
EP2AGX125EF35C4G β Last Time Buy
Specification Comparison
| Parameter | EP2AGX125EF35C4G | EP2AGX95EF35C4G |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,290.00 | $1,555.00 |
| Family | Arria II GX | Arria II GX |
| Logic Elements | 118,143 | β |
| Embedded Memory Bits | 8,315,904 | 6,839,296 bits (~6.5 Mbit) |
| Memory Blocks (M9K) | [DATA_NEEDED: M9K count] | β |
| Hardware Multipliers (18x18) | 452 | β |
| DSP Blocks | [DATA_NEEDED: DSP block count] | β |
| Transceiver Channels | 12 | β |
| Maximum Transceiver Data Rate | 6.375 Gbps | β |
| PCI Express Hard IP | Gen1/Gen2 x1/x4/x8 | β |
| Core Voltage | 0.9 V | 0.9 V nominal |
| User I/O Banks | [DATA_NEEDED: I/O bank count] | β |
| Maximum User I/O | [DATA_NEEDED: max user I/O count] | β |
| Process Technology | 40 nm | 40 nm TSMC low-power |
| Package | 1152-ball FC-FBGA (Flip-Chip) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C (commercial) |
| Mounting Type | Surface Mount | β |
| Configuration Method | SRAM-based, PS/FPP/JTAG | β |
| RoHS Status | Compliant | Compliant |
| Speed Grade | C4 | -4 (mid-speed) |
| Lead-Free | Yes | β |
| Logic Elements (LE) | β | 89,178 |
| Adaptive Logic Modules (ALM) | β | [DATA_NEEDED: ALM count from datasheet] |
| Embedded Memory Blocks (M9K/M144K) | β | [DATA_NEEDED: block count from datasheet] |
| Embedded 18x18 Multipliers | β | 616 |
| User I/Os | β | 452 |
| Transceiver Blocks | β | 4 (up to 3.75 Gbps) |
| PCIe Hard IP | β | Gen1/Gen2 (x1/x2/x4) |
| PLLs | β | 4 |
| Global Clock Networks | β | [DATA_NEEDED: per Arria II family datasheet] |
| Configuration Mode | β | Passive Serial, Fast Passive Parallel, JTAG |