EP2AGX190FF35I3N vs EP2AGX190FF35I3G Comparison
Detailed side-by-side comparison of EP2AGX190FF35I3N by Intel and EP2AGX190FF35I3G by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2AGX190FF35I3N - Arria II GX FPGA, 181K LE, 612 I/O, FCBGA-1152 | Intel
EP2AGX190FF35I3N β Last Time BuyAltera
EP2AGX190FF35I3G - Arria II GX FPGA 190K LE | Intel | Altera
EP2AGX190FF35I3G β Last Time BuySpecification Comparison
| Parameter | EP2AGX190FF35I3N | EP2AGX190FF35I3G |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,190.00 | $1,840.00 |
| Family | Arria II GX | Arria II GX |
| Logic Elements | 181,165 | β |
| Logic Array Blocks (LABs) | 7,612 | β |
| User I/O Pins | 612 | 612 |
| Process Technology | 40 nm TSMC low-power | β |
| Core Voltage | 0.9 V | 0.9 V |
| Transceiver Speed (max) | 3.75 Gbps (data rate, per family datasheet) | β |
| Total Transceivers | [DATA_NEEDED: transceiver count per FF35 package] | β |
| Embedded Memory | [DATA_NEEDED: M20K block count and total bits] | β |
| DSP Blocks | [DATA_NEEDED: variable-precision DSP block count] | β |
| PLLs | [DATA_NEEDED: PLL count for FF35 device] | [DATA_NEEDED: PLL count] |
| Package | 1152-ball FC-FBGA (FCBGA), 35 mm | 1152-ball FC-FBGA (FF35), 35 mm body |
| Mounting Type | Surface Mount | Surface Mount (flip-chip BGA) |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial, I3 grade) | -40 Β°C to +100 Β°C (industrial, suffix I) |
| Configuration | Serial / Parallel, supports encryption and remote update | β |
| RoHS Status | Compliant (per Altera/Intel product page) | Compliant (suffix G) |
| Logic Elements (LE) | β | 181,165 |
| Adaptive Logic Modules (ALM) | β | [DATA_NEEDED: ALM count] |
| Embedded Memory (bits) | β | 10,177,536 |
| Number of I/O Banks | β | [DATA_NEEDED: number of I/O banks] |
| Transceivers | β | 8 high-speed transceiver channels (multi-gigabit) |
| Embedded Multipliers | β | [DATA_NEEDED: 18x18 multiplier count] |
| I/O Voltage Standards | β | 1.2 V to 3.3 V (LVTTL, LVCMOS, LVDS, HSTL, SSTL) |
| Process Node | β | 40 nm |
| Speed Grade | β | 3 |
| Ball Pitch | β | [DATA_NEEDED: 1.0 mm (typical for FF35)] |
| Lead-Free | β | Yes |
| Programming Toolchain | β | Quartus II / Quartus Prime |