EP2S30F672I4 vs EP2S30F672C5N Comparison
Detailed side-by-side comparison of EP2S30F672I4 by Intel and EP2S30F672C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S30F672I4 | EP2S30F672C5N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $695.00 | $450.00 |
| Series | Stratix II | Stratix II |
| Manufacturer | Intel (formerly Altera) | β |
| Logic Elements | 33880 | 33,880 |
| Logic Array Blocks (LABs) | 1694 | 1694 |
| Total RAM Bits | 1369728 | β |
| Number of I/O | 500 | β |
| DSP Blocks | 12 (per datasheet, family range) | [DATA_NEEDED: DSP block count] |
| Number of PLLs | 6 | 4 |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | β |
| Operating Temperature | -40C to +100C (Industrial) | β |
| Mounting Type | Surface Mount | β |
| Package / Case | 672-BBGA, FCBGA (FBGA-672) | β |
| Package Dimensions | 35 x 35 mm | β |
| Ball Pitch | 1.0 mm | β |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | β |
| MSL Level | 3 (per JEDEC J-STD-020) | β |
| RoHS Status | [DATA_NEEDED: confirm RoHS compliance on part label] | β |
| Family Name | β | Stratix II |
| Embedded Memory (bits) | β | 1,369,728 |
| User I/O Count | β | 500 |
| Package | β | 672-ball FBGA (FineLine BGA) |
| Speed Grade | β | C5 (-5 commercial) |
| Supply Voltage (Core) | β | [DATA_NEEDED: core VCC value] |
| Operating Temperature Range | β | Commercial (0C to +85C) |
| Global Clock Networks | β | 16 |
| Configuration Method | β | Serial / Passive Parallel / Fast Passive Parallel |
| Lead-Free / RoHS | β | Yes (N suffix) |
| Architecture | β | Adaptive Logic Module (ALM) |
| Multipliers | β | [DATA_NEEDED: 18x18 multiplier count] |