EP3SE260F1517C4LN vs EP3SE260F1517I4LN Comparison

Detailed side-by-side comparison of EP3SE260F1517C4LN by Intel and EP3SE260F1517I4LN by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EP3SE260F1517C4LN EP3SE260F1517C4LN - Stratix III E FPGA 255K LE, 1517-BGA | Intel

EP3SE260F1517C4LN - Stratix III E FPGA 255K LE, 1517-BGA | Intel

EP3SE260F1517C4LN ⚠ Last Time Buy
Intel
EP3SE260F1517I4LN EP3SE260F1517I4LN - 260K LE Stratix III E FPGA, 1517-FCBGA | Intel

EP3SE260F1517I4LN - 260K LE Stratix III E FPGA, 1517-FCBGA | Intel

EP3SE260F1517I4LN ⚠ Last Time Buy

Specification Comparison

Parameter EP3SE260F1517C4LN EP3SE260F1517I4LN
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $1,450.00 $2,895.00
Series Stratix III E β€”
Family Stratix III E (Enhanced) Stratix III E (Enhanced)
Logic Elements 255,000 255,000
Number of LABs/CLBs 10,200 β€”
Total Memory Bits 16,672,768 (16.67 Mbit) β€”
Number of I/O 976 β€”
Number of Gates [DATA_NEEDED: gate count not published in web data] β€”
Voltage - Supply 0.9 V to 1.1 V core β€”
Operating Frequency 375 MHz to 450 MHz (per family) β€”
Process Technology 65 nm 40 nm CMOS
Package / Case 1517-BBGA, FCBGA (FC-FBGA) β€”
Mounting Type Surface Mount (flip-chip) β€”
Operating Temperature 0C to +85C (commercial grade per 'C' suffix) -40C to +100C (case, industrial)
Moisture Sensitivity Level (MSL) 3 (168 Hours) β€”
Packaging Tray β€”
Speed Grade C4 I4 (industrial, 4th tier)
Lead-Free / Halogen-Free Yes (LN suffix) β€”
RoHS Status Compliant β€”
Embedded Memory Bits β€” 16,672,768 bits (~2,044 KBytes)
Logic Array Blocks (LABs) β€” 10,200
User I/O Count β€” 976
Package β€” 1517-ball FCBGA (40 mm x 40 mm, 1.0 mm pitch)
Power Option β€” L (low-power)
Lead-Free / RoHS β€” Yes (N suffix)
Transceivers β€” Stratix III E family supports up to 24 transceivers up to 8.5 Gbps
DSP Blocks (18x18 multipliers) β€” Up to 384 (family-level, device-specific count not in provided data)
Partial Reconfiguration β€” Supported
Memory Interface Support β€” DDR3, DDR2, QDR II+ (hardened PHY)
Configuration Scheme β€” Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP), JTAG

Datasheets & Resources

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