EP3SE260H780C3 vs EP3SE260H780C3N Comparison
Detailed side-by-side comparison of EP3SE260H780C3 by Intel and EP3SE260H780C3N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N โ ActiveSpecification Comparison
| Parameter | EP3SE260H780C3 | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,180.00 | $1,325.00 |
| Device Family | Stratix III Enhanced (Stratix III E) | โ |
| Series | EP3SE | Stratixยฎ III E |
| Logic Elements | 255,000 | โ |
| Logic Array Blocks (LABs) | 10200 | โ |
| Embedded Memory | 16,672,768 bits (16.67 Mbit) | โ |
| User I/Os | 488 | 488 |
| Operating Voltage (Core) | 0.9 V | โ |
| Operating Voltage (Auxiliary) | 1.1 V | โ |
| Process Technology | 65 nm CMOS | 40 nm CMOS |
| Speed Grade | C3 | โ |
| Operating Temperature | Commercial, 0C to +85C | 0 ยฐC to +85 ยฐC (C grade, commercial) |
| Maximum Core Frequency | 500 MHz | [DATA_NEEDED: maximum core frequency MHz] |
| Package | 780-ball FCBGA (HBGA), flip-chip | 780-BBGA, FCBGA (H780) |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Moisture Sensitivity Level (MSL) | 3 (168 hours) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Packaging Type | Tray | โ |
| Configuration Memory Support | Fast passive parallel, JTAG, Active Serial | โ |
| RoHS Status | Compliant (per product listings) | Compliant (lead-free 'N' suffix) |
| Logic Elements (LE) | โ | 255,000 |
| Embedded Memory (bits) | โ | 16,672,768 |
| Number of LABs/CLBs | โ | 10,200 |
| Number of Pins / Balls | โ | 780 |
| Supply Voltage (VCCINT) | โ | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | โ | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | โ | [DATA_NEEDED: number of DSP blocks and precision] |
| Configuration Method | โ | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | โ | Altera Quartus II (legacy); Intel Quartus Prime |