EP3SL70F484I3N vs EP3SL70F484I3 Comparison
Detailed side-by-side comparison of EP3SL70F484I3N by Intel and EP3SL70F484I3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP3SL70F484I3N
EP3SL70F484I3N - 67.5K LE Stratix III L FPGA, 484-FBGA | Intel
EP3SL70F484I3N NrndIntel
EP3SL70F484I3
EP3SL70F484I3 - Stratix III L FPGA, 67.5K LE, 484-FBGA | Intel
EP3SL70F484I3 β Last Time BuySpecification Comparison
| Parameter | EP3SL70F484I3N | EP3SL70F484I3 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $995.40 | $1,013.66 |
| Series | Stratix III L | β |
| Logic Elements / Cells | 67,500 | β |
| Number of LABs / CLBs | 2,700 | β |
| Total RAM Bits | 2,699,264 | β |
| Number of I/O | 296 | β |
| Package / Case | 484-BBGA, FCBGA | β |
| Supplier Device Package | 484-FBGA (23x23 mm) | β |
| Mounting Type | Surface Mount | β |
| Operating Temperature | -40C to +100C (TJ) | -40C to +100C (industrial) |
| Voltage - Supply | [DATA_NEEDED: core and I/O supply voltages] | β |
| Process Technology | 40 nm CMOS | β |
| DSP Blocks | [DATA_NEEDED: exact count for EP3SL70] | β |
| Number of Transceivers | [DATA_NEEDED: transceiver count for this speed grade] | β |
| Product Status | Obsolete (per Assypcb listing) | β |
| RoHS Status | [DATA_NEEDED: per datasheet] | Compliant |
| Moisture Sensitivity Level (MSL) | [DATA_NEEDED: MSL rating] | β |
| Speed Grade | 3 | -3 (mid-tier) |
| Temperature Grade | Industrial (I) | β |
| Family | β | Stratix III L |
| Logic Elements | β | 67,500 |
| Adaptive Logic Modules (ALMs) | β | 33,000 |
| Logic Array Blocks (LABs) | β | 2,700 |
| Total Embedded Memory | β | 2,699,264 bits (337 KB) |
| M9K Memory Blocks | β | 288 |
| M144K Memory Blocks | β | 12 |
| DSP Blocks (18x18 multipliers) | β | 384 |
| User I/O Pins | β | 296 |
| Transceivers | β | Up to 12 (3.75 Gbps) [DATA_NEEDED: confirm exact count for F484 package] |
| PLLs | β | 8 (4 enhanced PLLs + 4 fast PLLs) |
| Process Node | β | TSMC 40 nm |
| Package | β | 484-ball Flip-Chip BGA (FBGA-484), 1.0 mm pitch |
| Configuration Modes | β | FPP, AS, PS, JTAG, AES encryption |
| Design Software | β | Quartus II (legacy) |