EP610DC-15 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP610DC-15 by Altera and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-15 | EP610DC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $10.40 |
| Product Family | Classic EPLD (EP610) | β |
| Architecture | UV-erasable CMOS PAL-type | β |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | 4 (4 product terms per macrocell) |
| Dedicated Inputs | 20 | 16 |
| Bidirectional I/O Pins | 16 | β |
| Total Product Terms | 160 | β |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 30 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0C to 70C (commercial) | Commercial (0C to +70C) |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CERDIP (windowed) |
| Mounting Type | Through-Hole | Through-Hole |
| Programming Method | JEDEC fuse map, UV erasure | β |
| Technology | CMOS | CMOS EPROM |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Family | β | EP610 (Classic Device Family) |
| Usable Gates | β | 300 |
| Maximum Pipelined Clock Frequency | β | 100 MHz |
| I/O Pins | β | 16 (with output enable) |
| Speed Grade | β | -30 (30 ns tPD) |
| Programmability | β | UV-erasable, windowed EPROM |
| Security Bit | β | Yes (protects design after programming) |
| Output Modes | β | Registered and Combinatorial |