EP610DC-15 vs EP610DI-25 Comparison
Detailed side-by-side comparison of EP610DC-15 by Altera and EP610DI-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-15 | EP610DI-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $9.95 |
| Product Family | Classic EPLD (EP610) | β |
| Architecture | UV-erasable CMOS PAL-type | β |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | β |
| Dedicated Inputs | 20 | 4 |
| Bidirectional I/O Pins | 16 | β |
| Total Product Terms | 160 | β |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 25 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V nominal |
| Operating Temperature | 0C to 70C (commercial) | Industrial (per "I" suffix) |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | β |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Programming Method | JEDEC fuse map, UV erasure | β |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Part Family | β | Classic EPLD |
| Maximum Pipelined Clock Frequency | β | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | β | 16 (bidirectional) |
| Total User I/O | β | 20 |
| Package Type | β | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Pin Count | β | 24 |
| Speed Grade Suffix | β | 25 = 25 ns |
| Compliance | β | RoHS status unknown (legacy 1990s part) |