EP610DI-25 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610DI-25 by Intel and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-25 | EP610DC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $7.95 |
| Part Family | Classic EPLD | β |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 15 ns (speed grade -15) |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | β |
| I/O Pins | 16 (bidirectional) | β |
| Dedicated Inputs | 4 | 20 |
| Total User I/O | 20 | β |
| Technology | CMOS EPROM (UV-erasable) | CMOS |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | β |
| Pin Count | 24 | β |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Operating Temperature | Industrial (per "I" suffix) | 0C to 70C (commercial) |
| Speed Grade Suffix | 25 = 25 ns | β |
| Compliance | RoHS status unknown (legacy 1990s part) | β |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Logic Expanders | β | 4 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Package | β | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | β | JEDEC fuse map, UV erasure |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |