EP610DI-25 vs EP610DI-30N Comparison
Detailed side-by-side comparison of EP610DI-25 by Intel and EP610DI-30N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-25 | EP610DI-30N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $17.80 |
| Part Family | Classic EPLD | β |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 30 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | β |
| I/O Pins | 16 (bidirectional) | β |
| Dedicated Inputs | 4 | β |
| Total User I/O | 20 | β |
| Technology | CMOS EPROM (UV-erasable) | β |
| Supply Voltage (VCC) | 5 V nominal | 5 V Β±5% |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | β |
| Pin Count | 24 | 24 |
| Mounting Type | Through-Hole (DIP) | Through-hole (DIP) |
| Operating Temperature | Industrial (per "I" suffix) | -40Β°C to +85Β°C (industrial) |
| Speed Grade Suffix | 25 = 25 ns | β |
| Compliance | RoHS status unknown (legacy 1990s part) | β |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Family | β | Altera Classic EP610 |
| Usable Gates | β | 300 |
| Maximum Frequency | β | 33.3 MHz (system); 100 MHz (pipelined) |
| Package | β | CDIP-24 (Ceramic DIP, windowed) |
| Process Technology | β | CMOS |
| Programming Method | β | UV-erasable (windowed ceramic) |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |