EP610DI-30N vs EP610DI-25 Comparison
Detailed side-by-side comparison of EP610DI-30N by Altera and EP610DI-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-30N | EP610DI-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.80 | $9.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EP610 | β |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 30 ns | 25 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | β |
| Supply Voltage (VCC) | 5 V Β±5% | 5 V nominal |
| Package | CDIP-24 (Ceramic DIP, windowed) | β |
| Pin Count | 24 | 24 |
| Operating Temperature | -40Β°C to +85Β°C (industrial) | Industrial (per "I" suffix) |
| Process Technology | CMOS | β |
| Programming Method | UV-erasable (windowed ceramic) | β |
| Mounting Type | Through-hole (DIP) | Through-Hole (DIP) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Part Family | β | Classic EPLD |
| Maximum Pipelined Clock Frequency | β | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | β | 16 (bidirectional) |
| Dedicated Inputs | β | 4 |
| Total User I/O | β | 20 |
| Technology | β | CMOS EPROM (UV-erasable) |
| Package Type | β | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Speed Grade Suffix | β | 25 = 25 ns |
| Compliance | β | RoHS status unknown (legacy 1990s part) |