EP610IDC-10 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610IDC-10 by Intel and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-10 | EP610DC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $7.95 |
| Device Family | Altera Classic EPLD | β |
| Logic Capacity | 300 usable gates | β |
| Macrocell Count | 16 macrocells | β |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | β |
| Maximum Counter Frequency (fCNT) | 100 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V |
| I/O Logic Compatibility | 100% TTL emulation | β |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS |
| Package Type | 24-pin Ceramic DIP (CDIP) | β |
| Dedicated Inputs | 4 | 20 |
| I/O Pins | 20 | β |
| Operating Temperature Range | 0 Β°C to +70 Β°C (commercial) | β |
| Programmable Interconnect | Yes (on-chip) | β |
| In-System Programmability | Yes (via MAX+PLUS II) | β |
| Boundary-Scan Test | Yes (per device documentation) | β |
| RoHS Status | [DATA_NEEDED: RoHS status of CDIP-10 variant] | [DATA_NEEDED: RoHS status] |
| Mounting Type | Through-hole | Through-Hole |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Macrocells | β | 16 |
| Logic Expanders | β | 4 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Propagation Delay (tPD) | β | 15 ns (speed grade -15) |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Operating Temperature | β | 0C to 70C (commercial) |
| Package | β | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | β | JEDEC fuse map, UV erasure |