EP610IDC-10 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP610IDC-10 by Intel and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-10 | EP610DC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $10.40 |
| Device Family | Altera Classic EPLD | β |
| Logic Capacity | 300 usable gates | β |
| Macrocell Count | 16 macrocells | β |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | β |
| Maximum Counter Frequency (fCNT) | 100 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal) | β |
| I/O Logic Compatibility | 100% TTL emulation | β |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS EPROM |
| Package Type | 24-pin Ceramic DIP (CDIP) | β |
| Dedicated Inputs | 4 | 16 |
| I/O Pins | 20 | 16 (with output enable) |
| Operating Temperature Range | 0 Β°C to +70 Β°C (commercial) | β |
| Programmable Interconnect | Yes (on-chip) | β |
| In-System Programmability | Yes (via MAX+PLUS II) | β |
| Boundary-Scan Test | Yes (per device documentation) | β |
| RoHS Status | [DATA_NEEDED: RoHS status of CDIP-10 variant] | β |
| Mounting Type | Through-hole | Through-Hole |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Family | β | EP610 (Classic Device Family) |
| Macrocells | β | 16 |
| Logic Expanders | β | 4 (4 product terms per macrocell) |
| Usable Gates | β | 300 |
| Maximum Pipelined Clock Frequency | β | 100 MHz |
| Propagation Delay (tPD) | β | 30 ns |
| Package | β | 24-pin CERDIP (windowed) |
| Speed Grade | β | -30 (30 ns tPD) |
| Programmability | β | UV-erasable, windowed EPROM |
| Security Bit | β | Yes (protects design after programming) |
| Output Modes | β | Registered and Combinatorial |
| Operating Temperature | β | Commercial (0C to +70C) |