EP610ILI-12 vs EP610IDC-10 Comparison

Detailed side-by-side comparison of EP610ILI-12 by Altera and EP610IDC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610ILI-12 EP610IDC-10
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $8.85
Family Classic EPLD (EP610) β€”
Usable Gates 300 β€”
Macro Cells 16 β€”
Speed Grade (tpd) 12 ns β€”
Supply Voltage (Vcc) 5 V (4.75 V to 5.25 V) β€”
Supply Voltage (Vpp) [DATA_NEEDED: Vpp programming voltage] β€”
Operating Frequency (max) 83.3 MHz β€”
Logic Elements [DATA_NEEDED: exact LE count] β€”
User I/O Pins [DATA_NEEDED: I/O pin count] β€”
Dedicated Inputs 4 4
Technology CMOS EPROM CMOS, UV-erasable (windowed ceramic)
Operating Temperature -40C to +85C (industrial grade) β€”
Package 28-pin PLCC (J-Lead) β€”
Mounting Type Surface Mount Through-hole
Programmable Security Bit Yes β€”
TTL Compatibility 100 TTL emulation β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status of CDIP-10 variant]
MSL Level [DATA_NEEDED: MSL rating] β€”
Device Family β€” Altera Classic EPLD
Logic Capacity β€” 300 usable gates
Macrocell Count β€” 16 macrocells
Pin-to-Pin Logic Delay (tpd) β€” 10 ns
Maximum Counter Frequency (fCNT) β€” 100 MHz
Supply Voltage (VCC) β€” 5 V (nominal)
I/O Logic Compatibility β€” 100% TTL emulation
Package Type β€” 24-pin Ceramic DIP (CDIP)
I/O Pins β€” 20
Operating Temperature Range β€” 0 Β°C to +70 Β°C (commercial)
Programmable Interconnect β€” Yes (on-chip)
In-System Programmability β€” Yes (via MAX+PLUS II)
Boundary-Scan Test β€” Yes (per device documentation)

Datasheets & Resources

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