EP610LC-30 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP610LC-30 by Intel and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-30 | EP610DC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $10.40 |
| Family | Classic EPLD (EP610) | EP610 (Classic Device Family) |
| Macro Cells | 16 | β |
| Logic Gates | Equivalent to 300 gates (typical) | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Pipelined Data Rate | up to 100 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Programming Voltage (VPP) | 13 V nominal | β |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM |
| Package | 24-pin CERDIP / PDIP | 24-pin CERDIP (windowed) |
| Operating Temperature | 0 C to +70 C (commercial) / -55 C to +125 C (military) | Commercial (0C to +70C) |
| Erase/Program Cycles | 1000 typical | β |
| Mounting Type | Through-Hole | Through-Hole |
| Output Type | CMOS tri-state (programmable) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Logic Compatibility | TTL and CMOS | β |
| Turbo Mode | Yes (registered path bypass) | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 16 |
| Logic Expanders | β | 4 (4 product terms per macrocell) |
| Usable Gates | β | 300 |
| Maximum Pipelined Clock Frequency | β | 100 MHz |
| Propagation Delay (tPD) | β | 30 ns |
| Dedicated Inputs | β | 16 |
| I/O Pins | β | 16 (with output enable) |
| Speed Grade | β | -30 (30 ns tPD) |
| Programmability | β | UV-erasable, windowed EPROM |
| Security Bit | β | Yes (protects design after programming) |
| Output Modes | β | Registered and Combinatorial |