EP910DC-35 vs EP910DC-40 Comparison

Detailed side-by-side comparison of EP910DC-35 by Altera and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910DC-35 EP910DC-40
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.95 $13.95
Device Type UV-Erasable CMOS PLD (PAL-type) β€”
Family Classic EPLD EP910 β€”
Architecture PAL-type sum-of-products AND-OR array PAL-type AND/OR, UV-erasable CMOS
Usable Gates 900 gates β€”
Macrocells 24 24
Product Terms 240 240 maximum
Dedicated Inputs 12 12
I/O Pins 24 β€”
Total Inputs 36 β€”
Propagation Delay (tpd) 35 ns β€”
Maximum Clock Frequency 37 MHz (typical, internal) β€”
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial) β€”
Package 40-pin CDIP (Ceramic DIP) with quartz window DIP-40 (ceramic, through-hole)
Lead Pitch 2.540 mm β€”
Termination Style Through-Hole β€”
Programming Method JEDEC fuse map via device programmer; UV erase UV-erase + EPROM programmer; on-board logic test circuitry
Technology CMOS, UV-erasable EPROM cell β€”
RoHS Status Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: rohs_status]
Lifecycle Obsolete / last-time-buy from authorized distributors β€”
Device Family β€” Classic EPLD (EP910 series)
Bidirectional I/O Pins β€” 24
Total Inputs to Logic Array β€” 36
Maximum Propagation Delay (tPD) β€” 40 ns
Maximum Operating Frequency (fMAX) β€” 25 MHz
Global Clocks β€” 2
Supply Voltage β€” 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) β€” 0 Β°C to 70 Β°C
Mounting Type β€” Through-Hole

Datasheets & Resources

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