EP910DC-35 vs EP910IDI-15 Comparison
Detailed side-by-side comparison of EP910DC-35 by Altera and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DC-35 | EP910IDI-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.95 | $29.00 |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | CPLD (Complex Programmable Logic Device) |
| Family | Classic EPLD EP910 | Classic EPLD |
| Architecture | PAL-type sum-of-products AND-OR array | β |
| Usable Gates | 900 gates | β |
| Macrocells | 24 | 24 |
| Product Terms | 240 | β |
| Dedicated Inputs | 12 | β |
| I/O Pins | 24 | β |
| Total Inputs | 36 | β |
| Propagation Delay (tpd) | 35 ns | β |
| Maximum Clock Frequency | 37 MHz (typical, internal) | β |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | -40C to +85C (industrial, "I" grade) |
| Package | 40-pin CDIP (Ceramic DIP) with quartz window | 40-pin CDIP (CerDIP) with quartz window |
| Lead Pitch | 2.540 mm | β |
| Termination Style | Through-Hole | β |
| Programming Method | JEDEC fuse map via device programmer; UV erase | β |
| Technology | CMOS, UV-erasable EPROM cell | CMOS EPROM |
| RoHS Status | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | β |
| Logic Gates | β | 450 gates |
| Maximum User I/O Pins | β | 36 |
| Pin-to-Pin Propagation Delay (tpd) | β | 15 ns |
| Maximum Counter Frequency | β | 66.6 MHz |
| Program/Erase Method | β | UV-erasable windowed CerDIP |
| Mounting Type | β | Through-hole (DIP) |
| Macrocells Configurable As | β | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | β | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | β | Altera Logic Programmer card |
| Logic Family Compatibility | β | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |