EP910DC-40 vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910DC-40 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910DC-40 EP910DC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $13.95 $10.95
Device Family Classic EPLD (EP910 series) β€”
Architecture PAL-type AND/OR, UV-erasable CMOS PAL-type sum-of-products AND-OR array
Macrocells 24 24
Dedicated Inputs 12 12
Bidirectional I/O Pins 24 β€”
Total Inputs to Logic Array 36 β€”
Product Terms 240 maximum 240
Maximum Propagation Delay (tPD) 40 ns β€”
Maximum Operating Frequency (fMAX) 25 MHz β€”
Global Clocks 2 β€”
Supply Voltage 5 V (typical for Classic EPLD family) β€”
Operating Temperature (Commercial) 0 Β°C to 70 Β°C β€”
Package DIP-40 (ceramic, through-hole) 40-pin CDIP (Ceramic DIP) with quartz window
Mounting Type Through-Hole β€”
RoHS Status [DATA_NEEDED: rohs_status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Programming Method UV-erase + EPROM programmer; on-board logic test circuitry JEDEC fuse map via device programmer; UV erase
Device Type β€” UV-Erasable CMOS PLD (PAL-type)
Family β€” Classic EPLD EP910
Usable Gates β€” 900 gates
I/O Pins β€” 24
Total Inputs β€” 36
Propagation Delay (tpd) β€” 35 ns
Maximum Clock Frequency β€” 37 MHz (typical, internal)
Supply Voltage (Vcc) β€” 4.75 V to 5.25 V (5 V nominal)
Operating Temperature β€” 0 Β°C to +70 Β°C (commercial)
Lead Pitch β€” 2.540 mm
Termination Style β€” Through-Hole
Technology β€” CMOS, UV-erasable EPROM cell
Lifecycle β€” Obsolete / last-time-buy from authorized distributors

Datasheets & Resources

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