EP910DM-40 vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910DM-40 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910DM-40 EP910DC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $21.00 $10.95
Product Type UV Erasable Programmable Logic Device (EPLD) β€”
Family Altera Classic EP910 Classic EPLD EP910
Architecture PAL-type AND/OR with global programmable interconnect bus PAL-type sum-of-products AND-OR array
Macrocells 24 24
Dedicated Inputs 36 12
Dedicated Outputs 24 β€”
Bidirectional I/O Lines 24 β€”
Product Terms 240 240
Propagation Delay (tPD) 40 ns β€”
External Clocks 2 β€”
Process Technology CMOS β€”
Package 40-pin Ceramic DIP (Cerdip) with UV window 40-pin CDIP (Ceramic DIP) with quartz window
Mounting Type Through-Hole (DIP) β€”
Operating Temperature [DATA_NEEDED: operating temperature range] 0 Β°C to +70 Β°C (commercial)
Supply Voltage 5 V β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Programming Interface JEDEC-standard fuse-map / UV erasure β€”
Device Type β€” UV-Erasable CMOS PLD (PAL-type)
Usable Gates β€” 900 gates
I/O Pins β€” 24
Total Inputs β€” 36
Propagation Delay (tpd) β€” 35 ns
Maximum Clock Frequency β€” 37 MHz (typical, internal)
Supply Voltage (Vcc) β€” 4.75 V to 5.25 V (5 V nominal)
Lead Pitch β€” 2.540 mm
Termination Style β€” Through-Hole
Programming Method β€” JEDEC fuse map via device programmer; UV erase
Technology β€” CMOS, UV-erasable EPROM cell
Lifecycle β€” Obsolete / last-time-buy from authorized distributors

Datasheets & Resources

Browse All Products Create BOM Request Quote