EP910DM-40 vs EP910IDI-15 Comparison
Detailed side-by-side comparison of EP910DM-40 by Altera and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DM-40 | EP910IDI-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.00 | $29.00 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | β |
| Family | Altera Classic EP910 | Classic EPLD |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | β |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | β |
| Dedicated Outputs | 24 | β |
| Bidirectional I/O Lines | 24 | β |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 40 ns | β |
| External Clocks | 2 | β |
| Process Technology | CMOS | β |
| Package | 40-pin Ceramic DIP (Cerdip) with UV window | 40-pin CDIP (CerDIP) with quartz window |
| Mounting Type | Through-Hole (DIP) | Through-hole (DIP) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial, "I" grade) |
| Supply Voltage | 5 V | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Gates | β | 450 gates |
| Maximum User I/O Pins | β | 36 |
| Pin-to-Pin Propagation Delay (tpd) | β | 15 ns |
| Maximum Counter Frequency | β | 66.6 MHz |
| Supply Voltage (Vcc) | β | 5 V |
| Technology | β | CMOS EPROM |
| Program/Erase Method | β | UV-erasable windowed CerDIP |
| Macrocells Configurable As | β | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | β | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | β | Altera Logic Programmer card |
| Logic Family Compatibility | β | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |