EP910DM883B vs EP910DC-35 Comparison
Detailed side-by-side comparison of EP910DM883B by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910DM883B
EP910DM883B - 24-Macrocell CMOS EPLD, 40ns, CDIP-40 | Altera
EP910DM883B ObsoleteAltera
EP910DC-35
EP910DC-35 - 35ns 900-Gate CMOS UV PLD DIP-40 | Intel / Altera
EP910DC-35 ObsoleteSpecification Comparison
| Parameter | EP910DM883B | EP910DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $10.95 |
| Manufacturer | Altera (now part of Intel) | β |
| Family | Classic EPLD - EP910 Series | Classic EPLD EP910 |
| Device Type | Erasable Programmable Logic Device (EPLD) | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | PAL-type AND-OR-NOT, CMOS | PAL-type sum-of-products AND-OR array |
| Macrocells | 24 | 24 |
| Inputs | 36 | β |
| Outputs | 24 | β |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns (typical) | β |
| Maximum Clock Frequency | 25 MHz | 37 MHz (typical, internal) |
| Supply Voltage (VCC) | 5 V | β |
| Programming Voltage (VPP) | 12.5 V (UV-erase window) | β |
| Operating Temperature | -55 Β°C to +125 Β°C (military) | 0 Β°C to +70 Β°C (commercial) |
| Package | CDIP-40 (Ceramic DIP, 40-pin) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Mounting Type | Through-Hole (DIP) | β |
| MIL Processing | MIL-STD-883B Class B | β |
| Configuration Memory | UV-erasable EPROM | β |
| Logic Elements | Combinational + Registered | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Usable Gates | β | 900 gates |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Total Inputs | β | 36 |
| Propagation Delay (tpd) | β | 35 ns |
| Supply Voltage (Vcc) | β | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | β | 2.540 mm |
| Termination Style | β | Through-Hole |
| Programming Method | β | JEDEC fuse map via device programmer; UV erase |
| Technology | β | CMOS, UV-erasable EPROM cell |
| Lifecycle | β | Obsolete / last-time-buy from authorized distributors |