EP910IDI-15 vs EP910DC-35 Comparison
Detailed side-by-side comparison of EP910IDI-15 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910IDI-15
EP910IDI-15 - 24-Macrocell Classic EPLD 15ns | Intel / Altera
EP910IDI-15 ObsoleteAltera
EP910DC-35
EP910DC-35 - 35ns 900-Gate CMOS UV PLD DIP-40 | Intel / Altera
EP910DC-35 ObsoleteSpecification Comparison
| Parameter | EP910IDI-15 | EP910DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $29.00 | $10.95 |
| Family | Classic EPLD | Classic EPLD EP910 |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable CMOS PLD (PAL-type) |
| Logic Gates | 450 gates | β |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | β |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | β |
| Maximum Counter Frequency | 66.6 MHz | β |
| Supply Voltage (Vcc) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM cell |
| Program/Erase Method | UV-erasable windowed CerDIP | β |
| Package | 40-pin CDIP (CerDIP) with quartz window | 40-pin CDIP (Ceramic DIP) with quartz window |
| Operating Temperature | -40C to +85C (industrial, "I" grade) | 0 Β°C to +70 Β°C (commercial) |
| Mounting Type | Through-hole (DIP) | β |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | β |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | β |
| Programming Hardware | Altera Logic Programmer card | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | β |
| Architecture | β | PAL-type sum-of-products AND-OR array |
| Usable Gates | β | 900 gates |
| Product Terms | β | 240 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Total Inputs | β | 36 |
| Propagation Delay (tpd) | β | 35 ns |
| Maximum Clock Frequency | β | 37 MHz (typical, internal) |
| Lead Pitch | β | 2.540 mm |
| Termination Style | β | Through-Hole |
| Programming Method | β | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | β | Obsolete / last-time-buy from authorized distributors |