EP910ILC-15N vs EP910ILI-25 Comparison
Detailed side-by-side comparison of EP910ILC-15N by Altera and EP910ILI-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoleteSpecification Comparison
| Parameter | EP910ILC-15N | EP910ILI-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $7.25 |
| Family | Classic | β |
| Product Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Logic Gates | 450 | β |
| Macro Cells | 24 | β |
| Maximum Propagation Delay (tPD) | 15 ns | β |
| Maximum Operating Frequency | 66.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| User I/O Pins | 36 | β |
| Dedicated Input Pins | 16 | β |
| Package | PLCC-44 (J-lead, surface mount) | PLCC-44 (windowed ceramic, J-lead) |
| Mounting Type | Surface Mount | β |
| Operating Temperature | 0 C to +70 C (commercial) | -40C to +85C (Industrial) |
| Process Technology | CMOS EPROM (one-time programmable) | β |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| RoHS Status | Compliant | Non-compliant (windowed ceramic package) |
| Programming | EPROM / JTAG (Classic EP-series) | β |
| Series | β | EP910 (Classic EPLD) |
| Macrocells | β | 24 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Product Terms | β | 240 (maximum) |
| Propagation Delay (tPD) | β | 25 ns |
| Technology | β | CMOS, EPROM |
| Architecture | β | PAL-type with global interconnect bus |
| Operating Voltage | β | 5 V (4.75 V to 5.25 V) |
| Programming Method | β | UV-erasable (windowed), MAX+PLUS II programmer |
| Logic Test Circuitry | β | On-board JTAG-compatible test |