EP910ILI-25 vs EP910ILC-15N Comparison
Detailed side-by-side comparison of EP910ILI-25 by Altera and EP910ILC-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoleteSpecification Comparison
| Parameter | EP910ILI-25 | EP910ILC-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.25 | $9.85 |
| Product Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Series | EP910 (Classic EPLD) | β |
| Macrocells | 24 | β |
| Dedicated Inputs | 12 | β |
| I/O Pins | 24 | β |
| Product Terms | 240 (maximum) | β |
| Propagation Delay (tPD) | 25 ns | β |
| Technology | CMOS, EPROM | β |
| Architecture | PAL-type with global interconnect bus | β |
| Package | PLCC-44 (windowed ceramic, J-lead) | PLCC-44 (J-lead, surface mount) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | β |
| Operating Temperature | -40C to +85C (Industrial) | 0 C to +70 C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | β |
| Logic Test Circuitry | On-board JTAG-compatible test | β |
| RoHS Status | Non-compliant (windowed ceramic package) | Compliant |
| Family | β | Classic |
| Logic Gates | β | 450 |
| Macro Cells | β | 24 |
| Maximum Propagation Delay (tPD) | β | 15 ns |
| Maximum Operating Frequency | β | 66.6 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | β | 36 |
| Dedicated Input Pins | β | 16 |
| Mounting Type | β | Surface Mount |
| Process Technology | β | CMOS EPROM (one-time programmable) |
| JTAG Support | β | IEEE 1149.1 boundary-scan |
| Programming | β | EPROM / JTAG (Classic EP-series) |