EP910JC-30 vs EP910PI-20 Comparison

Detailed side-by-side comparison of EP910JC-30 by Intel and EP910PI-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910JC-30 EP910PI-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $9.75
Family Classic EPLD (MAX-style) β€”
Propagation Delay (tpd) 30 ns β€”
Maximum Internal Frequency (Fmax) 33.3 MHz β€”
Macrocells 24 24
Inputs 36 β€”
Product Terms 240 β€”
Outputs 10 dedicated β€”
Supply Voltage (Vcc) 5 V β€”
Technology CMOS EPROM, UV-erasable CMOS EPROM (UV-erasable windowed variants available)
Package 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) PDIP-40 (PI suffix)
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Supply Current (Icc) [DATA_NEEDED: Icc typical / maximum] β€”
Mounting Type Surface Mount (socket-mountable) Through-Hole
RoHS Status [DATA_NEEDED: RoHS compliance] unknown
Logic Blocks 24 macrocells (AND/OR array architecture) β€”
Device Family β€” Altera Classic EPLD Family
Propagation Delay (tPD) β€” 20 ns
Supply Voltage (VCC) β€” 5 V (+/- 5%)
Configuration Method β€” Non-volatile EPROM (no boot PROM required)
Dedicated Inputs β€” 12
Bidirectional I/O Pins β€” 24
Maximum Counter Frequency β€” 125 MHz
Output Drive Current (IOL) β€” 24 mA (TTL-compatible)
Programmable Polarity β€” Yes (XOR gate per macrocell)
Macrocell Flip-Flop β€” Yes (D-type, programmable)
Power Dissipation β€” [DATA_NEEDED: typical power dissipation in mW]
Programming Interface β€” JEDEC file via Altera programming hardware
MIL-STD-883 Variant β€” EP910DM/883B (separate part number)

Datasheets & Resources

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