EP910LC-30 vs EP910DC-35 Comparison
Detailed side-by-side comparison of EP910LC-30 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910DC-35
EP910DC-35 - 35ns 900-Gate CMOS UV PLD DIP-40 | Intel / Altera
EP910DC-35 ObsoleteSpecification Comparison
| Parameter | EP910LC-30 | EP910DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.50 | $10.95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable CMOS PLD (PAL-type) |
| Macrocell Count | 24 | β |
| Propagation Delay (tPD) | 30 ns (max) | β |
| Maximum Toggle Frequency | 62 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | β |
| Process Technology | CMOS (EPROM-based) | β |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| I/O Pin Count | 24 | β |
| Dedicated Input Pins | 36 (including I/O) | β |
| Product Terms per Macrocell | Up to 16 | β |
| Programming Technology | UV-erasable EPROM cell | β |
| Development Tool | Altera MAX+PLUS II | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Family | β | Classic EPLD EP910 |
| Architecture | β | PAL-type sum-of-products AND-OR array |
| Usable Gates | β | 900 gates |
| Macrocells | β | 24 |
| Product Terms | β | 240 |
| Dedicated Inputs | β | 12 |
| I/O Pins | β | 24 |
| Total Inputs | β | 36 |
| Propagation Delay (tpd) | β | 35 ns |
| Maximum Clock Frequency | β | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | β | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | β | 0 Β°C to +70 Β°C (commercial) |
| Package | β | 40-pin CDIP (Ceramic DIP) with quartz window |
| Lead Pitch | β | 2.540 mm |
| Termination Style | β | Through-Hole |
| Programming Method | β | JEDEC fuse map via device programmer; UV erase |
| Technology | β | CMOS, UV-erasable EPROM cell |
| Lifecycle | β | Obsolete / last-time-buy from authorized distributors |