EP910LC-30 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910LC-30 by Altera and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30 | EP910DC-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.50 | $13.95 |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocell Count | 24 | β |
| Propagation Delay (tPD) | 30 ns (max) | β |
| Maximum Toggle Frequency | 62 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | β |
| Process Technology | CMOS (EPROM-based) | β |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| I/O Pin Count | 24 | β |
| Dedicated Input Pins | 36 (including I/O) | β |
| Product Terms per Macrocell | Up to 16 | β |
| Programming Technology | UV-erasable EPROM cell | β |
| Development Tool | Altera MAX+PLUS II | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Device Family | β | Classic EPLD (EP910 series) |
| Architecture | β | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | β | 24 |
| Dedicated Inputs | β | 12 |
| Bidirectional I/O Pins | β | 24 |
| Total Inputs to Logic Array | β | 36 |
| Product Terms | β | 240 maximum |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Operating Frequency (fMAX) | β | 25 MHz |
| Global Clocks | β | 2 |
| Supply Voltage | β | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | β | 0 Β°C to 70 Β°C |
| Package | β | DIP-40 (ceramic, through-hole) |
| Mounting Type | β | Through-Hole |
| Programming Method | β | UV-erase + EPROM programmer; on-board logic test circuitry |