EP910LC-30 vs EP910JC-30 Comparison
Detailed side-by-side comparison of EP910LC-30 by Altera and EP910JC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30 | EP910JC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.50 | $9.75 |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocell Count | 24 | β |
| Propagation Delay (tPD) | 30 ns (max) | β |
| Maximum Toggle Frequency | 62 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | β |
| Process Technology | CMOS (EPROM-based) | β |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| I/O Pin Count | 24 | β |
| Dedicated Input Pins | 36 (including I/O) | β |
| Product Terms per Macrocell | Up to 16 | β |
| Programming Technology | UV-erasable EPROM cell | β |
| Development Tool | Altera MAX+PLUS II | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Family | β | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | β | 30 ns |
| Maximum Internal Frequency (Fmax) | β | 33.3 MHz |
| Macrocells | β | 24 |
| Inputs | β | 36 |
| Product Terms | β | 240 |
| Outputs | β | 10 dedicated |
| Supply Voltage (Vcc) | β | 5 V |
| Technology | β | CMOS EPROM, UV-erasable |
| Package | β | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Operating Temperature | β | [DATA_NEEDED: operating temperature range] |
| Supply Current (Icc) | β | [DATA_NEEDED: Icc typical / maximum] |
| Mounting Type | β | Surface Mount (socket-mountable) |
| Logic Blocks | β | 24 macrocells (AND/OR array architecture) |