EP910LC-30Y vs EP910LC-30 Comparison
Detailed side-by-side comparison of EP910LC-30Y by Altera and EP910LC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910LC-30Y | EP910LC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.40 | $22.50 |
| Family | Altera Classic EPLD | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 24 | β |
| Usable Gates | 450 | β |
| Pin-to-Pin Delay (tPD) | 30 ns | β |
| Counter Frequency (fMAX) | 100 MHz (family maximum) | β |
| Supply Voltage | 5 V (TTL-compatible) | β |
| Process Technology | CMOS, UV-erasable / OTP | CMOS (EPROM-based) |
| Package | PLCC-44 | β |
| Operating Temperature | Commercial 0C to +70C | β |
| Speed/Power Grade | LC (low-power, 30ns) | β |
| Processing Flow | Y (extended reliability) | β |
| Logic Compatibility | 100% TTL emulation | β |
| Mounting Type | Surface Mount (PLCC socket) | β |
| RoHS Status | [DATA_NEEDED: RoHS status not specified in retrieved data] | [DATA_NEEDED: RoHS status] |
| Macrocell Count | β | 24 |
| Propagation Delay (tPD) | β | 30 ns (max) |
| Maximum Toggle Frequency | β | 62 MHz |
| Supply Voltage (VCC) | β | 5 V (nominal, TTL) |
| Package Type | β | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | β | Commercial (0C to +70C) |
| I/O Pin Count | β | 24 |
| Dedicated Input Pins | β | 36 (including I/O) |
| Product Terms per Macrocell | β | Up to 16 |
| Programming Technology | β | UV-erasable EPROM cell |
| Development Tool | β | Altera MAX+PLUS II |
| MSL Level | β | [DATA_NEEDED: MSL level] |