EP910LC44-35 vs EP910LI-35BF Comparison

Detailed side-by-side comparison of EP910LC44-35 by Intel and EP910LI-35BF by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP910LI-35BF

EP910LI-35BF - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Altera

EP910LI-35BF Obsolete

Specification Comparison

Parameter EP910LC44-35 EP910LI-35BF
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $19.95 $23.95
Family Classic EPLD (OT sub-family) β€”
Architecture PAL-type AND/OR array β€”
Macrocells 24 24
Usable Gates 450 β€”
Propagation Delay (tPD) 35 ns (max) β€”
Maximum Frequency (fMAX) 28.6 MHz β€”
Total Inputs 36 β€”
I/O Pins 24 β€”
Global Clocks 2 β€”
Supply Voltage (VCC) 5 V (single supply) 5 V (nominal)
Operating Temperature 0C to +70C (commercial) β€”
Package 44-pin PLCC (J-leaded) 44-pin PLCC (J-lead)
Mounting Type Surface Mount β€”
Process Technology CMOS β€”
Programmability UV-erasable (windowed ceramic) β€”
Device Family β€” Altera Classic EPLD
Part Number Base β€” EP910
Logic Density β€” 450 usable gates
Maximum Pin-to-Pin Delay (tpd) β€” 35 ns
Maximum Toggle Frequency (fmax) β€” 28.6 MHz
Operating Temperature Range β€” Industrial (LI suffix)
Technology β€” CMOS, UV-erasable
Programming Method β€” EPROM/UV-erase programmer (Altera Classic algorithm)
Output Polarity Control β€” Programmable XOR per macrocell
Flip-Flop Type β€” Selectable D/T/JK/SR per macrocell
TTL Compatibility β€” 100% TTL emulation
Compliance / EOL Status β€” Obsolete - last-time buy exhausted; second-source via Rochester Electronics

Datasheets & Resources

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