EP910PC-35 vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910PC-35 by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP910PC-35

EP910PC-35 - 35ns 24-Macrocell EPLD | Altera | Classic EPLD

EP910PC-35 Obsolete

Specification Comparison

Parameter EP910PC-35 EP910DC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.70 $10.95
Family Classic EPLD Classic EPLD EP910
Device Type EPLD (Erasable Programmable Logic Device) UV-Erasable CMOS PLD (PAL-type)
Macrocells 24 24
I/O Pins 24 24
Dedicated Inputs 12 12
Total Inputs 36 36
Product Terms 240 240
Propagation Delay (tPD) 35 ns β€”
Maximum Counter Frequency 37 MHz β€”
Internal Performance Frequency 100 MHz β€”
Technology CMOS, UV-erasable/OTP CMOS, UV-erasable EPROM cell
Supply Voltage 5 V β€”
Operating Temperature [DATA_NEEDED: operating temperature range] 0 Β°C to +70 Β°C (commercial)
Package 40-pin PDIP (Plastic DIP) 40-pin CDIP (Ceramic DIP) with quartz window
Mounting Type Through-Hole β€”
Architecture PAL-type sum-of-products, AND/OR array PAL-type sum-of-products AND-OR array
Programming Method UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools JEDEC fuse map via device programmer; UV erase
Compliance / RoHS [DATA_NEEDED: RoHS status - legacy part] β€”
Usable Gates β€” 900 gates
Propagation Delay (tpd) β€” 35 ns
Maximum Clock Frequency β€” 37 MHz (typical, internal)
Supply Voltage (Vcc) β€” 4.75 V to 5.25 V (5 V nominal)
Lead Pitch β€” 2.540 mm
Termination Style β€” Through-Hole
RoHS Status β€” Non-compliant (ceramic DIP with Pb-bearing lead finish)
Lifecycle β€” Obsolete / last-time-buy from authorized distributors

Datasheets & Resources

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