EP910PC-35 vs EP910PI-35T Comparison
Detailed side-by-side comparison of EP910PC-35 by Altera and EP910PI-35T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP910PI-35T
EP910PI-35T - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Altera
EP910PI-35T ObsoleteSpecification Comparison
| Parameter | EP910PC-35 | EP910PI-35T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.70 | $11.15 |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | β |
| Dedicated Inputs | 12 | β |
| Total Inputs | 36 | β |
| Product Terms | 240 | β |
| Propagation Delay (tPD) | 35 ns | β |
| Maximum Counter Frequency | 37 MHz | β |
| Internal Performance Frequency | 100 MHz | β |
| Technology | CMOS, UV-erasable/OTP | β |
| Supply Voltage | 5 V | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Package | 40-pin PDIP (Plastic DIP) | 40-pin PDIP (Plastic DIP) |
| Mounting Type | Through-Hole | Through-Hole |
| Architecture | PAL-type sum-of-products, AND/OR array | β |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | UV-erasable, EPROM technology |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | β |
| Usable Gates | β | 450 |
| Pin-to-Pin Logic Delay (tpd) | β | 35 ns |
| Counter Frequency (fCNT) | β | 28.6 MHz |
| Supply Voltage (VCC) | β | 5 V |
| I/O Logic Compatibility | β | 100% TTL emulation |
| Process Technology | β | CMOS |
| On-board Test Circuitry | β | Yes (logic test mode for AC verification) |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance status] |
| MSL Level | β | [DATA_NEEDED: MSL level] |