EP910PI-20 vs EP910JC-30 Comparison
Detailed side-by-side comparison of EP910PI-20 by Altera and EP910JC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-20 | EP910JC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $9.75 |
| Device Family | Altera Classic EPLD Family | β |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | β |
| Package | PDIP-40 (PI suffix) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Mounting Type | Through-Hole | Surface Mount (socket-mountable) |
| Supply Voltage (VCC) | 5 V (+/- 5%) | β |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS EPROM, UV-erasable |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | β |
| Dedicated Inputs | 12 | β |
| Bidirectional I/O Pins | 24 | β |
| Maximum Counter Frequency | 125 MHz | β |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | β |
| Programmable Polarity | Yes (XOR gate per macrocell) | β |
| Macrocell Flip-Flop | Yes (D-type, programmable) | β |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | β |
| Programming Interface | JEDEC file via Altera programming hardware | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | β |
| Family | β | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | β | 30 ns |
| Maximum Internal Frequency (Fmax) | β | 33.3 MHz |
| Inputs | β | 36 |
| Product Terms | β | 240 |
| Outputs | β | 10 dedicated |
| Supply Voltage (Vcc) | β | 5 V |
| Supply Current (Icc) | β | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | β | 24 macrocells (AND/OR array architecture) |