EPC1441LC20N vs EPC1213LC20 Comparison

Detailed side-by-side comparison of EPC1441LC20N by Intel and EPC1213LC20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPC1441LC20N

EPC1441LC20N - 440Kb OTP Config PROM, 20-PLCC | Intel/Altera

EPC1441LC20N Obsolete
Intel
EPC1213LC20

EPC1213LC20 - 212Kb OTP Config PROM 20-PLCC | Altera / Intel

EPC1213LC20 Obsolete

Specification Comparison

Parameter EPC1441LC20N EPC1213LC20
Brand Intel Intel
Category Memory ICs EEPROM
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.95 $7.40
Memory Type OTP EPROM (One-Time Programmable) OTP Configuration PROM (Flash-based)
Memory Size 440 Kbit 212 Kbit
Organization 55 K x 8 bit β€”
Interface Serial, 4-wire (nCS, DCLK, DATA, nINIT_CONF) Serial (Altera FPGA configuration protocol)
Configuration Clock (DCLK) 8 MHz maximum β€”
Programming Interface JTAG (IEEE 1149.1) / Altera Programming Unit β€”
Supply Voltage 3.3 V (typical) β€”
Package 20-PLCC (J-Lead, 9 x 9 mm) 20-PLCC (J-lead, 9x9 mm)
Operating Temperature 0 C to +70 C (commercial) 0C to +70C (Commercial)
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Cascadable Yes (nCS daisy-chain) β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
MSL Level [DATA_NEEDED: MSL level] β€”
Lead-Free [DATA_NEEDED: lead-free status] β€”
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Maximum Configuration Clock β€” 6 MHz
Supply Voltage (Core) β€” 5.0 V
I/O Voltage Tolerance β€” 3.3 V / 5.0 V
Programmability β€” One-Time Programmable (OTP) via IEEE 1149.1 JTAG
In-System Programmability β€” Yes (5.0 V and 3.3 V ISP)
Compression Support β€” Yes (FPGA decompresses bitstream during load)
Package Code β€” QCCJ

Datasheets & Resources

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