EPC144ILC-20 vs EPC1441LC20N Comparison
Detailed side-by-side comparison of EPC144ILC-20 by Altera and EPC1441LC20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC144ILC-20
EPC144ILC-20 - 440kb OTP Configuration PROM | Altera | PLCC-20
EPC144ILC-20 β Last Time BuyIntel
EPC1441LC20N
EPC1441LC20N - 440Kb OTP Config PROM, 20-PLCC | Intel/Altera
EPC1441LC20N ObsoleteSpecification Comparison
| Parameter | EPC144ILC-20 | EPC1441LC20N |
|---|---|---|
| Brand | Altera | Intel |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.85 | $7.95 |
| Memory Type | OTP Configuration PROM (one-time programmable) | OTP EPROM (One-Time Programmable) |
| Memory Size | 440 kb (kilobits) | 440 Kbit |
| Configuration Interface | Serial (Altera proprietary PS mode) | β |
| Supply Voltage | 5.0 V (typical) | 3.3 V (typical) |
| Standby Current | < 50 uA (CMOS standby) | β |
| Programmable | No (factory-programmed by Altera or distributor) | β |
| Package | 20-pin PLCC (J-lead) | 20-PLCC (J-Lead, 9 x 9 mm) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Compatible FPGA Families | Cyclone, ACEX 1K, APEX 20K, MAX 7000-series | β |
| Configuration Mode Support | PS (passive serial) and FPP (fast passive parallel) | β |
| JTAG Interface | Not present | β |
| End-of-Life Status | Last-time-buy (per Altera product change notifications) | β |
| Lead-Free / RoHS | Depends on date code; non-RoHS vintage stock common | β |
| Programming Method | Altera dedicated PROM programmer hardware | β |
| Data Retention | Permanent (anti-fuse OTP cell, no retention concern) | β |
| Pin Count | 20 | β |
| Mounting Type | Surface Mount (PLCC J-lead) | Surface Mount (PLCC socket compatible) |
| Organization | β | 55 K x 8 bit |
| Interface | β | Serial, 4-wire (nCS, DCLK, DATA, nINIT_CONF) |
| Configuration Clock (DCLK) | β | 8 MHz maximum |
| Programming Interface | β | JTAG (IEEE 1149.1) / Altera Programming Unit |
| Supported FPGA Families | β | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Cascadable | β | Yes (nCS daisy-chain) |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |