EPC16QC100N vs EPC16SI16N Comparison
Detailed side-by-side comparison of EPC16QC100N by Altera and EPC16SI16N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC16QC100N
EPC16QC100N - 16Mb FPGA Configuration PROM, 100-PQFP | Altera
EPC16QC100N ObsoleteIntel
EPC16SI16N
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N β Last Time BuySpecification Comparison
| Parameter | EPC16QC100N | EPC16SI16N |
|---|---|---|
| Brand | Altera | Intel |
| Category | Memory ICs | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $24.10 | $4.35 |
| Memory Size | 16 Mbit (16,777,216 bits) | 16 Mb (16,777,216 bits) |
| Programmable Type | In System Programmable | β |
| Configuration Clock Frequency | 33 MHz max | β |
| On-Chip Decompression | Yes (supports compressed bitstreams) | β |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | β |
| Access Time | 90 ns typical | β |
| Flash Read Bandwidth | 160 Mbps (16-bit DQ at 10 MHz) | β |
| Configuration Interface | FPP / PS / AS via dedicated FPGA pins | β |
| JTAG (IEEE 1149.1) ISP | Supported | β |
| Operating Temperature | 0 C to 70 C | -40 C to +85 C (industrial, 'SI' suffix) |
| Package | 100-pin PQFP (20 x 14 mm) | 16-pin SOIC (300 mil, 'SI' suffix) |
| Mounting Type | Surface Mount | Surface Mount |
| Lead Free | Yes (per datasheet) | β |
| Packaging | Tray | β |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | β |
| Memory Type | β | Non-volatile flash (enhanced configuration device) |
| Interface | β | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) |
| Programming Interface | β | JTAG (IEEE 1149.1 boundary scan) |
| Maximum Operating Frequency | β | 40 MHz (fast configuration mode) |
| Operating Supply Voltage | β | 3.3 V (typ) |
| Lead-Free / Finish | β | Lead-free (matte tin), 'N' suffix |
| MSL Level | β | [DATA_NEEDED: MSL level] |
| RoHS Status | β | Compliant |
| In-System Programmability | β | Yes (via JTAG, multiple reprogramming cycles) |
| Compatible FPGA Series | β | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III |
| Configuration Daisy-Chaining | β | Supported (multiple devices / multiple FPGAs) |
| On-Chip Charge Pump | β | Integrated (no external VPP required) |