EPC16SI16N vs EPC16QC100N Comparison
Detailed side-by-side comparison of EPC16SI16N by Intel and EPC16QC100N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N β Last Time Buy
Specification Comparison
| Parameter | EPC16SI16N | EPC16QC100N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.35 | $24.10 |
| Memory Type | Non-volatile flash (enhanced configuration device) | β |
| Memory Size | 16 Mb (16,777,216 bits) | 16 Mbit (16,777,216 bits) |
| Interface | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) | β |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | β |
| Maximum Operating Frequency | 40 MHz (fast configuration mode) | β |
| Operating Supply Voltage | 3.3 V (typ) | β |
| Operating Temperature | -40 C to +85 C (industrial, 'SI' suffix) | 0 C to 70 C |
| Package | 16-pin SOIC (300 mil, 'SI' suffix) | 100-pin PQFP (20 x 14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Lead-Free / Finish | Lead-free (matte tin), 'N' suffix | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | Compliant | β |
| In-System Programmability | Yes (via JTAG, multiple reprogramming cycles) | β |
| Compatible FPGA Series | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III | β |
| Configuration Daisy-Chaining | Supported (multiple devices / multiple FPGAs) | β |
| On-Chip Charge Pump | Integrated (no external VPP required) | β |
| Programmable Type | β | In System Programmable |
| Configuration Clock Frequency | β | 33 MHz max |
| On-Chip Decompression | β | Yes (supports compressed bitstreams) |
| Supply Voltage (VCC) | β | 3.0 V to 3.6 V |
| Access Time | β | 90 ns typical |
| Flash Read Bandwidth | β | 160 Mbps (16-bit DQ at 10 MHz) |
| Configuration Interface | β | FPP / PS / AS via dedicated FPGA pins |
| JTAG (IEEE 1149.1) ISP | β | Supported |
| Lead Free | β | Yes (per datasheet) |
| Packaging | β | Tray |
| Supported FPGA Families | β | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |