EPC22C20N vs EPC21C20U Comparison

Detailed side-by-side comparison of EPC22C20N by Altera and EPC21C20U by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC22C20N EPC21C20U
Brand Altera Intel
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $11.40 $9.85
Manufacturer Intel (formerly Altera) Intel / Altera
Device Type Configuration PROM for SRAM-based LUT FPGAs β€”
Target FPGA Family FLEX 10K, FLEX 6000, APEX 20K series β€”
Configuration Interface Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) β€”
Programming Interface IEEE 1149.1 JTAG (in-system programmable) β€”
Supply Voltage 3.3 V or 5 V β€”
Package 20-pin PLCC (J-lead) 20-pin UBGA (Ultra FineLine BGA) - also called 20-pin FBGA
Package Marking Code EPC22C20N β€”
Pin Count 20 β€”
Mounting Type Surface Mount / Socket Surface Mount (BGA)
Operating Temperature [DATA_NEEDED: operating temperature range] -40 C to +85 C (industrial)
Bitstream Capacity [DATA_NEEDED: bitstream capacity in bits] β€”
Configuration Time [DATA_NEEDED: typical configuration time] β€”
RoHS Status [DATA_NEEDED: RoHS status] Compliant (per Intel/Altera product page)
Lead-Free Status [DATA_NEEDED: lead-free status] β€”
Lifecycle Status Obsolete (last-time-buy from Altera announced for legacy configuration devices) β€”
Product Type β€” Configuration Device (Boot Flash)
Memory Size β€” 20 Mbit (2.5 Mbyte)
Supply Voltage (VCC) β€” 3.0 V to 3.6 V (3.3 V typical)
Interface β€” Altera/Intel Passive Serial (PS) and Active Serial (AS), JTAG (IEEE 1149.1)
In-System Programmability β€” Yes (via JTAG)
Bitstream Compression Support β€” Yes
Cascade (Multi-Device) Support β€” Yes (nCASC daisy-chain)
Supported FPGA Families β€” APEX II, APEX 20KE, APEX 20KC, Mercury, Stratix, Cyclone, ACEX 1K, FLEX 10KE
Lead-Free β€” Yes
Configuration Mode β€” Passive Serial (PS) / Active Serial (AS) via FPGA controller

Datasheets & Resources

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